1. Field of the Invention
The present invention relates to a planarization method for a semiconductor device, and more particularly, to a planarization method for the semiconductor device that improves local and global flatness when manufacturing the semiconductor device.
2. Discussion of the Related Art
As semiconductor devices have become highly integrated, intervals between metal lines placed on the same layer have become narrower. Accordingly, manufacturing a semiconductor device with multiple-layer metal wiring becomes unavoidable. When forming the multiple-layer metal wiring, submicron intervals between the metal lines and between each layer of the metal lines should be filled in with an insulation material without any voids. In a photolithographic process, the margin of the depth of focus should be maintained by decreasing global topological differences over a wafer that occur due to a process of making a multiple-layer metal wiring.
Currently, in order to fill in a submicron interval between the lines, a plasma enhanced oxidation film is deposited, a spin-on-glass photoresist is coated thereon, and an etchback is performed. A method for depositing an oxidation film by a high density plasma chemical vapor deposition method (HDP CVD) has recently become widely used. In order to decrease the global topological differences, a polymer such as a photoresist or Accuflo.TM. (a product manufactured by Allied Signal Co.), is coated onto the wafer, and an etchback is performed. Also, a chemical mechanical polishing method (CMP) has also become widely used recently.
FIGS. 1A and 1B are vertical cross-sectional views illustrating a conventional planarization method for a semiconductor device when forming the multiple-layer metal wiring. As shown in FIG. 1A, a conductive layer is deposited on a substrate 11, and the conductive layer is patterned, forming conductive lines 13. An oxidation film 15 is then deposited over the substrate 11 and the conductive lines 13 by using the HDP CVD method. Next, as shown in FIG. 1B, an upper surface of the oxidation film 15 is polished by using the CMP method, flattening the upper surface of the oxidation film 15.
The above method for depositing the oxidation film 15 by using the HDP CVD method has excellent hygroscopicity and is capable of filling in any gaps. However, since an additional step such as the CMP, as shown in FIG. 1B, is needed in order to decrease global topological differences after depositing the oxidation film 15, the manufacturing process of a semiconductor device becomes more complex and manufacturing cost increases.
Generally, when depositing and forming the oxidation film 15 by using the HDP CVD method, a DC bias or an RF bias, or a combination of the DC and RF biases is applied to a susceptor of a plasma etching reactor wherein a wafer is placed, which is different from the CVD method, so that deposition and sputtering can occur simultaneously. A sputtering effect exists, however, such that an etch rate of a surface slanted at 45 degrees to an incident ion is 3-4 times higher than that of a vertical surface, as shown in FIG. 1A. A lozenge-shaped portion 15a of oxidation film 15 is formed over a conductive line 13a with a width of approximately 2.0 .mu.m. The thickness of the lozenge-shaped portion of the oxidation film 15 is approximately the same as that of the oxidation film 15 formed over a region with no conductive lines 13. The oxidation film 15 fills in any gaps between the conductive lines 13. For example, if an oxidation film with a thickness of more than approximately 2.0 .mu.m is formed on a conductive line having a width greater than 2.0 .mu.m, a problem arises in that the lozenge-shaped oxidation film has a continuous flat shape. However, if the oxidation film 15 is formed over a conductive line 13b having a width of less than approximately 2.0 .mu.m, a small triangle-shaped profile 15b is formed. The height of the triangle becomes less as the ratio of deposition/sputtering rates is decreased, or the deposition thickness is increased, or the line width becomes narrower. If the line width is approximately 1.2 .mu.m, the ratio of the deposition/sputtering rates is approximately 3.2, and the oxidation film having a thickness of approximately 1.6 .mu.m is deposited by using the HDP CVD method, the triangle-shaped profile 15b almost disappears. When the oxidation film 15 is formed over a conductive line 13c, which has a width of less than approximately 2.0 .mu.m, as shown in FIG. 1A, the oxidation film 15 formed over the conductive line 13c becomes flattened and is almost level with the oxidation film 15 formed over the region having no conductive lines 13.
When the interval between the metal lines is greater than approximately 0.2 .mu.m, the thickness of an oxidation film deposited between the conductive lines 13 becomes substantially identical. This important phenomenon, obtained when depositing the oxidation film by using the HDP CVD method, can also be obtained by depositing and etching by a plasma CVD method. In addition, although the depositing method of the oxidation film 15 depends on the properties of the HDP CVD method, the phenomenon is not limited to the oxidation film.